Semiconductor device and method for fabricating the same

ABSTRACT

An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device having a buriedinterconnect buried in an interlayer dielectric film, and a method forfabricating the device.

In recent years. a high-integration semiconductor device such as anultra large scale integrated circuit (ULSI) has been required to enhancethe speed of signal transmission, and to be highly resistant tomigration intensified by an increase in power consumption. As aninterconnect material that meets such requirements, an aluminum alloyhas conventionally been used. However, in order to further enhance thespeed of signal transmission, low resistivity copper whose resistance toelectromigration is approximately ten times as high as that of aluminumhas lately been used as an interconnect material.

As processes particularly suitable for formation of copper interconnect,a single damascene process and a dual damascene process are known. Asingle damascene process repeats the steps of: filling a connectionhole, formed in an interlayer dielectric film, with a conductormaterial, and then removing an excess portion of the interconnectmaterial on the interlayer dielectric film by performingchemical/mechanical polishing (hereinafter, will be called “CMP”), thusforming a plug; and forming an upper interlayer dielectric film, fillingan interconnect groove, formed in the upper interlayer dielectric film,with a conductor material, and then performing CMP to form aninterconnect connected to the plug. On the other hand, a dual damasceneprocess repeats the step of: forming, in a single interlayer dielectricfilm, a connection hole and an interconnect groove overlapping with thisconnection hole, filling the connection hole and the interconnect groovewith an interconnect material at the same time, and then performing CMPto remove an excess portion of the interconnect material on theinterlayer dielectric film.

By using a damascene process, an interconnect can be easily formed evenif copper having difficulty in being patterned by dry etching is used asan interconnect material. In particular, a dual damascene process ismore advantageous than a single damascene process in that the step offilling a connection hole and an interconnect groove with aninterconnect material and the subsequent CMP step are each performedonly once in order to form an interconnect (see, for example, Document 1(Japanese Unexamined Patent Publication No. 2000-299376), and Document 2(Japanese Unexamined Patent Publication No. 2002-319617)).

FIG. 14 is a cross-sectional view illustrating the structure of aconventional semiconductor device including interconnect layers formedby performing a dual damascene process.

As shown in FIG. 14, the conventional semiconductor device includes: asubstrate 110 on which semiconductor elements (not shown) such as alarge number of transistors are formed; a lower interlayer dielectricfilm 111 provided on the substrate 110; a lower interconnect groove 113formed in the lower interlayer dielectric film 111; a lower barriermetal layer 114 formed along a wall surface of the lower interconnectgroove 113; a copper film 115 for filling the lower interconnect groove113; an upper interlayer dielectric film 117 provided on the lowerinterlayer dielectric film 111; a connection hole 118 formed in theupper interlayer dielectric film 117 and an upper interconnect groove119 formed thereon; an upper barrier metal layer 120 formed along wallsurfaces of the connection hole 118 and the upper interconnect groove119; and a copper film 121 for filling the connection hole 118 and theupper interconnect groove 119. A lower interconnect 116 is made up ofthe copper film 115 and the lower barrier metal layer 114, formed in thelower interlayer dielectric film 111, for filling the lower interconnectgroove 113. On the other hand, the upper interconnect groove 119 isformed in an extensive region of the upper interlayer dielectric film117 including the connection hole 118. Further, portions of the upperbarrier metal layer 120 and the copper film 121 filled in the connectionhole 118 constitute an upper plug 122 a, while another portions of theupper barrier metal layer 120 and the copper film 121 filled in theupper interconnect groove 119 constitute an upper interconnect 122 b.

SUMMARY OF THE INVENTION

However, a semiconductor device having a copper interconnect formed byperforming the above-described conventional damascene process or thelike presents the following problems.

As shown in FIG. 14, a void concentration region 125 is likely to beformed in a portion of the lower interconnect 116 (or the copper film115) in contact with the upper plug 122 a, in particular. Furthermore,since an electrical resistance in the void concentration region 125naturally increases, a contact resistance between the lower interconnect116 and the upper plug 122 a becomes excessive. As used herein, the“void concentration region” refers to the region where voids areconcentrated.

The mechanism of formation of the void concentration region 125 is notyet completely elucidated. However, the cause of formation of the voidconcentration region 125 is believed to be due to the fact that, sincethe larger the area of the lower interconnect 116, the more likely thevoid concentration region 125 is to be formed, stress is generated in aportion of the lower interconnect 116 in contact with the upper plug 122a, and this stress causes voids present in the copper film 115 to beconcentratedly gettered in the void concentration region 125.

In view of the above-described problems, an object of the presentinvention is to provide a semiconductor device that can suppressformation of a void concentration region in a portion of a lowerinterconnect in contact with an upper interconnect, and thus cansuppress an increase in contact resistance between the lower and upperinterconnects, and a method for fabricating such a device.

A first inventive semiconductor device includes: a lower interconnectthat is provided within a lower interconnect groove formed in a lowerinterlayer dielectric film, and that has convex or concave portions atleast at one of its bottom surface, side surfaces and upper surface; andan upper plug that passes through an upper interlayer dielectric filmand comes into contact with a part of the lower interconnect.

Thus, voids are also gettered by the convex or concave portions of thelower interconnect, and therefore, it becomes possible to suppress anincrease in contact resistance caused by the concentration of voids inthe contact area between the lower interconnect and the upper plug.

By providing concave portions, convex portions, or irregular-shapedconcave and convex portions at a bottom surface and/or side surfaces ofthe lower interconnect groove, the lower interconnect can be providedwith the convex or concave portions corresponding to the concaveportions, convex portions, or concave and convex portions of the lowerinterconnect groove.

If the lower interconnect includes a portion formed by a copper film, itbecomes possible to utilize, in particular, an advantage that areduction in interconnect resistance is achieved because of the use of acopper film.

A second inventive semiconductor device includes: a lower interconnectthat is provided within a lower interconnect groove formed in a lowerinterlayer dielectric film; a conductor film for covering the lowerinterconnect; and an upper plug that passes through an upper interlayerdielectric film and comes into contact with a part of the conductorfilm.

Thus, the concentration of stress in a portion of the lower interconnectlocated below the upper plug is relieved, and therefore, an increase incontact resistance can be suppressed.

A third inventive semiconductor device includes: a lower interconnectwhich is provided within a lower interconnect groove formed in a lowerinterlayer dielectric film, and into which dopant is implanted; and anupper plug that passes through an upper interlayer dielectric film andcomes into contact with a part of the lower interconnect.

Thus, voids are also gettered by the dopant present in the lowerinterconnect, and therefore, it becomes possible to suppress an increasein contact resistance caused by the concentration of voids in thecontact area between the lower interconnect and the upper plug.

In a first inventive method for fabricating a semiconductor device, alower interconnect groove having concave or convex portions at itsbottom surface is formed in a lower interlayer dielectric film, thelower interconnect groove is filled with a conductor material to form alower interconnect having convex or concave portions, and then an upperinterlayer dielectric film and an upper plug are formed.

By performing this method, the structure of the first inventivesemiconductor device can be easily obtained. More specifically, itbecomes possible to facilitate the fabrication of the semiconductordevice that can achieve the effect of relieving the concentration ofvoids in the contact area between the upper plug and the lowerinterconnect.

As a method for forming an interconnect groove having concave portionsat least partially at its bottom surface, the present invention mayemploy any of: a method for forming concave or convex portions at abottom surface of a lower interconnect groove by performing etchingusing an etching mask; a method for forming concave or convex portionsat side surfaces of a lower interconnect groove by etching side surfacesof a lower interlayer dielectric film having a second layer; and amethod for performing etching such that a deposition film remains onbottom and side surfaces of a lower interconnect groove, andsubsequently etching portions of a lower interlayer dielectric filmexposed to the lower interconnect groove, thus forming irregular-shapedconcave and convex portions at the bottom and side surfaces of the lowerinterconnect groove.

In a second inventive method for fabricating a semiconductor device, alower interconnect buried in a lower interconnect groove is formed, astress-relieving conductor film is formed over the lower interconnectgroove, and then an upper interlayer dielectric film and an upper plugare formed.

By performing this method, the structure of the second inventivesemiconductor device can be easily obtained. More specifically, itbecomes possible to facilitate the fabrication of the semiconductordevice that can achieve the effect of relieving the concentration ofvoids in the contact area between the upper plug and the lowerinterconnect.

In a third inventive method for fabricating a semiconductor device, alower interconnect groove is formed in a lower interlayer dielectricfilm, the lower interconnect groove is filled with a conductor materialto form a lower interconnect, dopant ions are implanted into the lowerinterconnect, and then an upper interlayer dielectric film and an upperplug are formed.

By performing this method, the structure of the third inventivesemiconductor device can be easily obtained. More specifically, itbecomes possible to facilitate the fabrication of the semiconductordevice that can achieve the effect of relieving the concentration ofvoids in the contact area between the upper plug and the lowerinterconnect.

The inventive semiconductor devices or the inventive fabricating methodsthereof each relieve the concentration of voids in the contact areabetween the lower interconnect and the upper plug. Thus, the presentinvention can provide a semiconductor device in which contact resistancein its interconnect layer is low, and a method for fabricating such asemiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating the structure of asemiconductor device according to a first embodiment of the presentinvention.

FIGS. 2A through 2D are cross-sectional views and plan viewsillustrating the first half of the process for fabricating thesemiconductor device of the first embodiment.

FIGS. 3A through 3C are cross-sectional views illustrating the latterhalf of the process for fabricating the semiconductor device of thefirst embodiment.

FIG. 4 is a cross-sectional view illustrating the structure of asemiconductor device according to a second embodiment of the presentinvention.

FIGS. 5A through 5D are cross-sectional views illustrating the processfor fabricating the semiconductor device of the second embodiment.

FIG. 6 is a cross-sectional view illustrating the structure of asemiconductor device according to a third embodiment of the presentinvention.

FIGS. 7A through 7D are cross-sectional views illustrating the processfor fabricating the semiconductor device of the third embodiment.

FIG. 8 is a cross-sectional view illustrating the structure of asemiconductor device according to a fourth embodiment of the presentinvention.

FIGS. 9A through 9D are cross-sectional views illustrating the processfor fabricating the semiconductor device of the fourth embodiment.

FIG. 10 is a cross-sectional view illustrating the structure of asemiconductor device according to a fifth embodiment of the presentinvention.

FIGS. 11A through 11D are cross-sectional views illustrating the processfor fabricating the semiconductor device of the fifth embodiment.

FIG. 12 is a cross-sectional view illustrating the structure of asemiconductor device according to a sixth embodiment of the presentinvention.

FIGS. 13A through 13C are cross-sectional views illustrating the processfor fabricating the semiconductor device of the sixth embodiment.

FIG. 14 is a cross-sectional view illustrating the structure of aconventional semiconductor device including interconnect layers formedby performing a dual damascene process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a cross-sectional view illustrating the structure of asemiconductor device according to a first embodiment of the presentinvention. As shown in FIG. 1, the semiconductor device of the presentembodiment includes: a substrate 10 on which semiconductor elements (notshown) such as a large number of transistors are formed; a lowerinterlayer dielectric film 11 provided on the substrate 10; a lowerinterconnect groove 13 formed in the lower interlayer dielectric film11; a lower barrier metal layer 14 formed along a wall surface of thelower interconnect groove 13; a copper film 15 for filling the lowerinterconnect groove 13 together with the barrier metal layer 14; asilicon nitride film 24 provided on the lower interlayer dielectric film11 and on the copper film 15; an upper interlayer dielectric film 17provided on the silicon nitride film 24; a connection hole 18 formed inthe upper interlayer dielectric film 17 and an upper interconnect groove19 formed thereon; an upper barrier metal layer 20 formed along wallsurfaces of the connection hole 18 and the upper interconnect groove 19;and a copper film 21 for filling the connection hole 18 and the upperinterconnect groove 19. A lower interconnect 16 is made up of the copperfilm 15 and the lower barrier metal layer 14 which fill the lowerinterconnect groove 13. On the other hand, the upper interconnect groove19 is formed in an extensive region of the upper interlayer dielectricfilm 17 including the connection hole 18. Further, portions of the upperbarrier metal layer 20 and the copper film 21 filled in the connectionhole 18 constitute an upper plug 22 a, while another portions of theupper barrier metal layer 20 and the copper film 21 filled in the upperinterconnect groove 19 constitute an upper interconnect 22 b. The upperplug 22 a passes through the silicon nitride film 24 and comes intocontact with the copper film 15 of the lower interconnect 16. The upperplug 22 a and the upper interconnect 22 b constitute an upperinterconnect layer 22.

The semiconductor device of the present embodiment is characterized inthat the lower surface of the lower interconnect groove 13, formed inthe lower interlayer dielectric film 11, is not flat, but has manyconcave portions 13 a, and the lower interconnect 16 has convex portions16 a having shapes corresponding to those of the concave portions 13 a.Even if the concave and convex portions 13 a and 16 a are provided onlyat a single position, the after-mentioned effects can be achieved. Inthe present embodiment, the lower interconnect 16 has a thickness of 0.3μm, for example, and a planar size of 0.38 μm×1.5 μm, i.e., a width of0.38 μm and a length of 1.5 μm, for example, while each concave portion13 a has a depth of 0.1 μm, for example, and a planar size of 0.2 μm×0.2μm, for example. The upper plug 22 a has a planar size of 0.2 μm×0.2 μm,for example. In the conventional structure, it is known that if thelower interconnect groove 13 has a width equal to or greater than 0.25μm and a length equal to or greater than 1 μm, a void concentrationregion is likely to be formed, in particular, in the lower interconnect16.

The present embodiment is applicable to the substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 1, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 16. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the shape of the lower interconnect16 described in the present embodiment.

In the semiconductor device of the present embodiment, the lowerinterconnect 16 is provided with the convex portions 16 a, and thusvoids are also gettered by the convex portions 16 a. Therefore, itbecomes possible to prevent voids from being concentratedly gettered ina region of the lower interconnect 16 in contact with the upper plug 22a. Thus, it is presumed that the convex portions 16 a achieve thefunction of gettering voids because stress is generated in the convexportions 16 a.

Hereinafter, a method for fabricating the semiconductor device accordingto the present embodiment will be described. FIGS. 2A through 2D arecross-sectional views and plan views illustrating the first half of theprocess for fabricating the semiconductor device of the presentembodiment. FIGS. 3A through 3C are cross-sectional views illustratingthe latter half of the process for fabricating the semiconductor deviceof the present embodiment. The cross-sectional views of thesemiconductor device are shown in the left part of FIGS. 2A through 2D,while the plan views of the semiconductor device are shown in the rightpart of FIGS. 2A through 2D.

First, in the step shown in FIG. 2A, a lower interlayer dielectric film11 formed of a BPSG film with a thickness of about 1 μm is deposited ona substrate 10, and then a lower interconnect groove 13 is formed in thelower interlayer dielectric film 11 by a known lithography and dryetching process. In this case, the depth D1 of the lower interconnectgroove 13, shown in the left part of FIG. 2A, is about 0.3 μm. On theother hand, the size L1 and size L2 of the lower interconnect groove 13,shown in the right part of FIG. 2A, are 0.38 μm and 1.5 μm,respectively.

Next, in the step shown in FIG. 2B, a lithography process is performedto form, on the lower interlayer dielectric film 11, a resist film Re1having a large number of openings Hole. In this case, the planar sizesL3 and L4 of the opening Hole, shown in the right part of FIG. 2B, areeach about 0.2 μm.

Subsequently, in the step shown in FIG. 2C, a dry etching process isperformed to remove portions of the lower interlayer dielectric film 11located below the openings Hole of the resist film Re1, thus formingconcave portions 13 a at the bottom surface of the lower interconnectgroove 13. In this case, the depth D2 of each concave portion 13 a,shown in the left part of FIG. 2C, is 0.1 μm, for example. Thereafter,an ashing process is performed to remove the resist film Re1.

In the present embodiment and a fourth embodiment described later, theconcave portions 13 a are each formed as a concave portion with abottom. Alternatively, if a conductor member is not exposed in regionsof the upper surface of the substrate 10 located directly below theconcave portions 13 a, the concave portions 13 a may pass through thelower interlayer dielectric film 11.

Next, in the step shown in FIG. 2D, a sputtering process, for example,is performed to deposit, on the lower interlayer dielectric film 11, alower barrier metal layer 14 formed of a TaN film with a thickness ofabout 50 nm, and then a copper film 15 is formed on the lower barriermetal layer 14 by a sputtering process, a CVD process, an electroplatingprocess or the like until the copper film 15 is filled in the lowerinterconnect groove 13. If an electroplating process is performed, aseed layer made of the same material as the interconnect material (whichis copper in the present embodiment) is formed. The TaN film has thefunction of suppressing diffusion of copper atoms.

Thereafter, in the step shown in FIG. 3A, the copper film 15 and thelower barrier metal layer 14 are planarized by a CMP process in whichthe copper film 15 and the lower barrier metal layer 14 are partiallyremoved until the upper surface of the lower interlayer dielectric film11 is exposed. Thus, a lower interconnect 16 made up of the copper film15 and the lower barrier metal layer 14 is formed. Further, at thebottom surface of the lower interconnect 16, downwardly projected convexportions 16 a are formed.

Subsequently, in the step shown in FIG. 3B, a silicon nitride film 24with a thickness of about 0.2 μm is formed on the lower interlayerdielectric film 11, and an upper interlayer dielectric film 17 formed ofa BPSG film with a thickness of about 1 μm is deposited on the siliconnitride film 24. Thereafter, a lithography and dry etching process isperformed to form a connection hole 18 that passes through the upperinterlayer dielectric film 17 and reaches the copper film 15 of thelower interconnect 16, and then an upper interconnect groove 19 isformed in a region of the upper interlayer dielectric film 17, includingthe connection hole 18, by performing a lithography and dry etchingprocess. By forming the silicon nitride film 24 so that it covers thecopper film 15 of the lower interconnect 16, oxidation of the copperfilm 15 can be prevented.

Next, in the step shown in FIG. 3C, a sputtering process, for example,is performed to deposit an upper barrier metal layer 20 having athickness of 50 nm and made of TaN across the wall surfaces of theconnection hole 18 and the upper interconnect groove 19 and the uppersurface of the upper interlayer dielectric film 17. Subsequently, acopper film 21 is deposited on the upper barrier metal layer 20 by asputtering process, a CVD process, an electroplating process or the likeuntil the copper film 21 is filled in the connection hole 18 and theupper interconnect groove 19. If an electroplating process is performed,a seed layer made of the same material as the interconnect material(which is copper in the present embodiment) is formed.

Thereafter, a CMP process is performed to partially remove the copperfilm 21 and the upper barrier metal layer 20 until the upper surface ofthe upper interlayer dielectric film 17 is exposed, thus obtaining thestructure of the semiconductor device shown in FIG. 1.

According to the semiconductor device fabricating method of the presentembodiment, the lower interconnect 16 having the convex portions 16 a atits bottom surface can be easily formed. Besides, in this structure, theconvex portions 16 a have the function of gettering voids. Therefore, itbecomes possible to suppress an increase in contact resistance caused byconcentrative gettering of voids in a region of the lower interconnect16 (within the copper film 15) in contact with the upper plug 22 a.

In the steps shown in FIGS. 2B and 2C, if etching is carried out byusing a lattice-shaped resist film Re1 as a mask, lattice-shaped convexportions are formed in the lower interlayer dielectric film 11, andtherefore, grooves (or concave portions) having shapes corresponding tothose of the lattice-shaped convex portions are formed in the lowerinterconnect 16. Even in that case, voids are gettered due to stressgenerated in the concave portions of the lower interconnect 16, thusachieving the same effects as those of the present embodiment. The sameholds true with regard to the fourth embodiment described later.

Second Embodiment

FIG. 4 is a cross-sectional view illustrating the structure of asemiconductor device according to a second embodiment of the presentinvention. As shown in FIG. 4, the semiconductor device of the presentembodiment includes: a substrate 10 on which semiconductor elements (notshown) such as a large number of transistors are formed; a lowerinterlayer dielectric film 11 provided on the substrate 10; a lowerinterconnect groove 13 formed in the lower interlayer dielectric film11; a lower barrier metal layer 14 formed along a wall surface of thelower interconnect groove 13; a copper film 15 for filling the lowerinterconnect groove 13; a silicon nitride film 24 provided on the lowerinterlayer dielectric film 11 and on the copper film 15; an upperinterlayer dielectric film 17 provided on the silicon nitride film 24; aconnection hole 18 formed in the upper interlayer dielectric film 17 andan upper interconnect groove 19 formed thereon; an upper barrier metallayer 20 formed along wall surfaces of the connection hole 18 and theupper interconnect groove 19; and a copper film 21 for filling theconnection hole 18 and the upper interconnect groove 19. A lowerinterconnect 16 is made up of the copper film 15 and the lower barriermetal layer 14 which fill the lower interconnect groove 13. On the otherhand, the upper interconnect groove 19 is formed in an extensive regionof the upper interlayer dielectric film 17 including the connection hole18. Further, portions of the upper barrier metal layer 20 and the copperfilm 21 filled in the connection hole 18 constitute an upper plug 22 a,while another portions of the upper barrier metal layer 20 and thecopper film 21 filled in the upper interconnect groove 19 constitute anupper interconnect 22 b. The upper plug 22 a passes through the siliconnitride film 24 and comes into contact with the copper film 15 of thelower interconnect 16. The upper plug 22 a and the upper interconnect 22b constitute an upper interconnect layer 22.

The semiconductor device of the present embodiment is characterized inthat wall surfaces (i.e., bottom and side surfaces) of the lowerinterconnect groove 13, formed in the lower interlayer dielectric film11, are not flat, but have irregular-shaped concave and convex portions13 b, and the lower interconnect 16 has concave and convex portions 16 bhaving irregular shapes corresponding to the shapes of the concave andconvex portions 13 b. Specifically, a plurality of concave portionsexist in the concave and convex portions 13 b of the lower interconnectgroove 13, and a plurality of convex portions exist in the concave andconvex portions 16 b of the lower interconnect 16. Herein, “irregularshapes” mean random shapes that are not identical for each interconnectof each semiconductor device.

Also in the present embodiment, the thickness and planar size of thelower interconnect 16 are similar to those of the lower interconnect 16of the first embodiment. In the conventional structure, it is known thatif the lower interconnect groove 13 has a width equal to or greater than0.25 μm and a length equal to or greater than 1 μm, a void concentrationregion is likely to be formed, in particular, in the lower interconnect16.

The present embodiment is applicable to the substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 4, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 16. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the shape of the lower interconnect16 described in the present embodiment.

In the semiconductor device of the present embodiment, the lowerinterconnect 16 is provided with the concave and convex portions 16 b,and thus voids are also gettered by the concave and convex portions 16b. Therefore, it becomes possible to prevent voids from beingconcentratedly gettered in a region of the lower interconnect 16 incontact with the upper plug 22 a. Thus, it is presumed that the concaveand convex portions 16 b achieve the function of gettering voids becausestress is generated in the concave and convex portions 16 b.

Hereinafter, a method for fabricating the semiconductor device accordingto the present embodiment will be described. FIGS. 5A through 5D arecross-sectional views illustrating the process for fabricating thesemiconductor device of the present embodiment.

First, in the step shown in FIG. 5A, a lower interlayer dielectric film11 formed of a BPSG film with a thickness of about 1 μm is deposited ona substrate 10, and thereafter a resist film Re2 is formed by a knownlithography process. Then, dry etching is performed using the resistfilm Re2 as a mask, thus forming a lower interconnect groove 13 in thelower interlayer dielectric film 11. In this case, the dry etching isperformed using CF₄ and CHF₃ as an etching gas at a gas pressure of 133pa and an RF power of 1 kw. Thus, after the etching has been finished,there remains a fluorocarbon film deposited nonuniformly on the wallsurface of the lower interconnect groove 13. The depth and planar sizeof the lower interconnect groove 13 may be the same as those of thelower interconnect groove 13 in the step shown in FIG. 2A according tothe first embodiment.

Next, in the step shown in FIG. 5B, wet etching is performed using ahydrofluoric acid-based etchant (such as HF or BHF), with thefluorocarbon film that has a non-uniform thickness remaining on the wallsurface of the lower interconnect groove 13. Thus, concave and convexportions 13 b are formed at the wall surface of the lower interconnectgroove 13. Alternatively, the fluorocarbon film (deposition film) may bepartially removed by oxygen plasma to partially expose the lowerinterlayer dielectric film 11, and then wet etching may be performedusing a hydrofluoric acid-based etchant.

Subsequently, in the step shown in FIG. 5C, a sputtering process, forexample, is performed to deposit, on the lower interlayer dielectricfilm 11, a lower barrier metal layer 14 formed of a TaN film with athickness of about 50 nm, and then a copper film 15 is formed on thelower barrier metal layer 14 by a sputtering process, a CVD process, anelectroplating process or the like until the copper film 15 is filled inthe lower interconnect groove 13. If an electroplating process isperformed, a seed layer made of the same material as the interconnectmaterial (which is copper in the present embodiment) is formed. The TaNfilm has the function of suppressing diffusion of copper atoms.

Thereafter, in the step shown in FIG. 5D, the copper film 15 and thelower barrier metal layer 14 are partially removed by a CMP processuntil the upper surface of the lower interlayer dielectric film 11 isexposed. Thus, a lower interconnect 16 made up of the copper film 15 andthe lower barrier metal layer 14 is formed. Further, at the bottom andside surfaces of the lower interconnect 16, irregular-shaped concave andconvex portions 16 b are formed.

Although the subsequent steps are not shown, the steps similar to thoseshown in FIGS. 3B and 3C according to the first embodiment are carriedout, thus obtaining the structure of the semiconductor device shown inFIG. 4.

According to the semiconductor device fabricating method of the presentembodiment, when the concave and convex portions 13 b are formed at thelower interconnect groove 13, it is possible to easily form the lowerinterconnect 16 having the irregular-shaped concave and convex portions16 b at its bottom surface, without adding a lithography processperformed in the first embodiment. Besides, in this structure, theconcave and convex portions 16 b have the function of gettering voids.Therefore, it becomes possible to suppress an increase in contactresistance caused by concentrative gettering of voids in a region of thelower interconnect 16 (within the copper film 15) in contact with theupper plug 22 a.

Third Embodiment

FIG. 6 is a cross-sectional view illustrating the structure of asemiconductor device according to a third embodiment of the presentinvention. As shown in FIG. 6, the semiconductor device of the presentembodiment includes: a substrate 10 on which semiconductor elements (notshown) such as a large number of transistors are formed; a lowerinterlayer dielectric film 11 provided on the substrate 10 andconsisting of a first layer 11 a with a low etch rate, a second layer 11b with a high etch rate, and a third layer 11 c with a low etch rate; alower interconnect groove 13 formed in the lower interlayer dielectricfilm 11; a lower barrier metal layer 14 formed along a wall surface ofthe lower interconnect groove 13; a copper film 15 for filling the lowerinterconnect groove 13; a silicon nitride film 24 provided on the lowerinterlayer dielectric film 11 and on the copper film 15; an upperinterlayer dielectric film 17 provided on the silicon nitride film 24; aconnection hole 18 formed in the upper interlayer dielectric film 17 andan upper interconnect groove 19 formed thereon; an upper barrier metallayer 20 formed along wall surfaces of the connection hole 18 and theupper interconnect groove 19; and a copper film 21 for filling theconnection hole 18 and the upper interconnect groove 19. A lowerinterconnect 16 is made up of the copper film 15 and the lower barriermetal layer 14 which fill the lower interconnect groove 13. On the otherhand, the upper interconnect groove 19 is formed in an extensive regionof the upper interlayer dielectric film 17 including the connection hole18. Further, portions of the upper barrier metal layer 20 and the copperfilm 21 filled in the connection hole 18 constitute an upper plug 22 a,while another portions of the upper barrier metal layer 20 and thecopper film 21 filled in the upper interconnect groove 19 constitute anupper interconnect 22 b. The upper plug 22 a passes through the siliconnitride film 24 and comes into contact with the copper film 15 of thelower interconnect 16. The upper plug 22 a and the upper interconnect 22b constitute an upper interconnect layer 22.

The semiconductor device of the present embodiment is characterized inthat side surfaces of the lower interconnect groove 13, formed in thelower interlayer dielectric film 11, are not flat, but side surfaces ofthe second layer 11 b have concave portions 13 c located outwardly ofside surfaces of the first layer 11 a and the third layer 11 c, and thelower interconnect 16 has convex portions 16 c buried in the concaveportions 13 c. Also in the present embodiment, the thickness and planarsize of the lower interconnect 16 are similar to those of the lowerinterconnect 16 of the first embodiment. Furthermore, the convexportions 16 c each have a longitudinal size of about 0.1 μm and aprojection of about 0.1 μm. In the conventional structure, it is knownthat if the lower interconnect groove 13 has a width equal to or greaterthan 0.25 μm and a length equal to or greater than 1 μm, a voidconcentration region is likely to be formed, in particular, in the lowerinterconnect 16.

The present embodiment is applicable to the substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 6, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 16. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the shape of the lower interconnect16 described in the present embodiment.

In the semiconductor device of the present embodiment, the lowerinterconnect 16 is provided at its side surfaces with the convexportions 16 c, and thus voids are also gettered by the convex portions16 c. Therefore, it becomes possible to prevent voids from beingconcentratedly gettered in a region of the lower interconnect 16 incontact with the upper plug 22 a. Thus, it is presumed that the convexportions 16 c achieve the function of gettering voids because stress isgenerated in the convex portions 16 c.

Unlike the present embodiment, if the second layer 11 b is made of aninsulating material with an etch rate lower than that of each of thefirst layer 11 a and the third layer 11 c, concave portions are to beformed at the side surfaces of the lower interconnect groove 13.However, even in such a case, voids can be gettered due to stressgenerated around the concave portions, and therefore, the effectssimilar to those of the present embodiment can be achieved. The sameholds true with regard to the fourth embodiment described later.

The third layer 11 c with a low etch rate does not necessarily have tobe provided on the second layer 11 b made of a material with a high etchrate. Alternatively, the lower interlayer dielectric film 11 may onlyconsist of the first layer 11 a and the second layer 11 b. Even in sucha case, since concave or convex portions are formed at the side surfacesof the lower interconnect groove 13, stress is generated in convex orconcave portions of the lower interconnect 16 having shapescorresponding to those of the concave or convex portions at the sidesurfaces of the lower interconnect groove 13, thus achieving the effectsof the present embodiment. The same holds true with regard to the fourthembodiment described later.

Hereinafter, a method for fabricating the semiconductor device accordingto the present embodiment will be described. FIGS. 7A through 7D arecross-sectional views illustrating the process for fabricating thesemiconductor device of the present embodiment.

First, in the step shown in FIG. 7A, a lower interlayer dielectric film11 consisting of: a first layer 11 a formed of a PSG film with athickness of about 0.8 μm; a second layer 11 b formed of an NSG filmwith a thickness of about 0.1 μm; and a third layer 11 c formed of a PSGfilm with a thickness of about 0.1 μm is deposited on a substrate 10,and thereafter a resist film Re3 is formed by a known lithographyprocess. Then, dry etching is performed using the resist film Re3 as amask, thus forming a lower interconnect groove 13 in the lowerinterlayer dielectric film 11. The depth and planar size of the lowerinterconnect groove 13 may be the same as those of the lowerinterconnect groove 13 in the step shown in FIG. 2A according to thefirst embodiment.

Next, in the step shown in FIG. 7B, wet etching is performed using ahydrofluoric acid-based etchant (such as HF or BHF), thus forming, atthe side surfaces of the lower interconnect groove 13, concave portions13 c each having a lateral depth of about 0.1 μm. The present embodimentutilizes the fact that the etch rate of an NSG film is higher than thatof a PSG film when a hydrofluoric acid-based etchant is used for wetetching.

The combination of materials for the first, second and third layers 11a, 11 b and 11 c of the lower interlayer dielectric film 11 may bechanged as follows. The lower interlayer dielectric film 11 may consistof: the first and third layers 11 a and 11 c each formed of an SiO₂film; and the second layer 11 b formed of an SiON film, and this lowerinterlayer dielectric film 11 may be wet-etched using a hydrofluoricacid-based etchant. The same holds true with regard to the fourthembodiment described later.

Subsequently, in the step shown in FIG. 7C, a sputtering process, forexample, is performed to deposit, on the lower interlayer dielectricfilm 11, a lower barrier metal layer 14 formed of a TaN film with athickness of about 50 nm, and then a copper film 15 is formed on thelower barrier metal layer 14 by a sputtering process, a CVD process, anelectroplating process or the like until the copper film 15 is filled inthe lower interconnect groove 13. If an electroplating process isperformed, a seed layer made of the same material as the interconnectmaterial (which is copper in the present embodiment) is formed. The TaNfilm has the function of suppressing diffusion of copper atoms.

Thereafter, in the step shown in FIG. 7D, the copper film 15 and thelower barrier metal layer 14 are partially removed by a CMP processuntil the upper surface of the lower interlayer dielectric film 11 isexposed. Thus, a lower interconnect 16 made up of the copper film 15 andthe lower barrier metal layer 14 is formed. Further, at the sidesurfaces of the lower interconnect 16, laterally projected convexportions 16 c are formed.

Although the subsequent steps are not shown, the steps similar to thoseshown in FIGS. 3B and 3C according to the first embodiment are carriedout, thus obtaining the structure of the semiconductor device shown inFIG. 6.

According to the semiconductor device fabricating method of the presentembodiment, when the concave portions 13 c are formed at the lowerinterconnect groove 13, it is possible to easily form the lowerinterconnect 16 having the convex portions 16 c at its side surfaces,without adding a lithography process performed in the first embodiment.Besides, in this structure, the convex portions 16 c have the functionof gettering voids. Therefore, it becomes possible to suppress anincrease in contact resistance caused by concentrative gettering ofvoids in a region of the lower interconnect 16 (within the copper film15) in contact with the upper plug 22 a.

In the present embodiment, the lower interlayer dielectric film 11consists of two kinds of insulating films having mutually different etchrates. Alternatively, the lower interlayer dielectric film 11 mayconsist of three or more kinds of insulating films.

Fourth Embodiment

FIG. 8 is a cross-sectional view illustrating the structure of asemiconductor device according to the fourth embodiment of the presentinvention. As shown in FIG. 8, the basic structure of the semiconductordevice according to the present embodiment is the same as that of thesemiconductor device according to the first through third embodiments.However, the semiconductor device of the fourth embodiment ischaracterized by having the features of both the first embodiment andthe third embodiment.

Specifically, the lower surface of a lower interconnect groove 13 formedin a lower interlayer dielectric film 11 is not flat, but has manyconcave portions 13 a, and a lower interconnect 16 has regular-shapedconvex portions 16 a buried in the concave portions 13 a. The concaveportions 13 a each have a depth of 0.1 μm, for example, and a planarsize of 0.2 μm×0.2 μm, for example.

Furthermore, the side surfaces of the lower interconnect groove 13formed in the lower interlayer dielectric film 11 are not flat, but haveconcave portions 13 c, and the lower interconnect 16 has convex portions16 c buried in the concave portions 13 c. The convex portions 16 c eachhave a longitudinal size of about 0.1 μm, and a projection of about 0.1μm.

Also in the present embodiment, the thickness and planar size of thelower interconnect 16 are similar to those of the lower interconnect 16according to the first embodiment. An upper plug 22 a has a planar sizeof 0.2 μm×0.2 μm, for example. In the conventional structure, it isknown that if the lower interconnect groove 13 has a width equal to orgreater than 0.25 μm and a length equal to or greater than 1 μm, a voidconcentration region is likely to be formed, in particular, in the lowerinterconnect 16.

The present embodiment is applicable to a substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 8, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 16. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the shape of the lower interconnect16 described in the present embodiment.

In the semiconductor device of the present embodiment, the lowerinterconnect 16 is provided, at its bottom and side surfaces, with theconvex portions 16 a and 16 c, respectively, and thus voids are alsogettered by the convex portions 16 a and 16 c. Therefore, it becomespossible to prevent voids from being concentratedly gettered in a regionof the lower interconnect 16 in contact with the upper plug 22 a.Accordingly, it becomes possible to achieve the function of distributingthe regions where voids are gettered, which is better than that achievedby the structure of the first embodiment or the third embodiment.

Hereinafter, a method for fabricating the semiconductor device of thefourth embodiment will be described. FIGS. 9A through 9D arecross-sectional views illustrating the process for fabricating thesemiconductor device of the present embodiment.

First, in the step shown in FIG. 9A, the steps similar to those shown inFIGS. 7A and 7B according to the third embodiment are carried out, thusforming concave portions 13 c at side surfaces of a lower interconnectgroove 13 in a lower interlayer dielectric film 11. Furthermore, alithography process is performed to form, on the lower interlayerdielectric film 11, a resist film Re4 having a large number of openingsHole. In this case, the planar size, the number, the location and thelike of the openings Hole are similar to those of the openings Holeshown in the left part and the right part of FIG. 2B according to thefirst embodiment.

Next, in the step shown in FIG. 9B, a dry etching process is performedto remove portions of the lower interlayer dielectric film 11 locatedbelow the openings Hole of the resist film Re4, thus forming concaveportions 13 a at the bottom surface of the lower interconnect groove 13.In this case, the depth of each concave portion 13 a is the same as thatof each concave portion 13 a according to the first embodiment.

Subsequently, in the step shown in FIG. 9C, an ashing process isperformed to remove the resist film Re4, and then a sputtering process,for example, is performed to deposit, on the lower interlayer dielectricfilm 11, a lower barrier metal layer 14 formed of a TaN film with athickness of about 50 nm. Thereafter, a copper film 15 is formed on thelower barrier metal layer 14 by a sputtering process, a CVD process, anelectroplating process or the like until the copper film 15 is filled inthe lower interconnect groove 13. If an electroplating process isperformed, a seed layer made of the same material as the interconnectmaterial (which is copper in the present embodiment) is formed. The TaNfilm has the function of suppressing diffusion of copper atoms.

Then, in the step shown in FIG. 9D, the copper film 15 and the lowerbarrier metal layer 14 are partially removed by a CMP process until theupper surface of the lower interlayer dielectric film 11 is exposed.Thus, a lower interconnect 16 made up of the copper film 15 and thelower barrier metal layer 14 is formed. Furthermore, downwardlyprojected convex portions 16 a and laterally projected convex portions16 c are formed at the bottom and side surfaces of the lowerinterconnect 16, respectively.

Although the subsequent steps are not shown, the steps similar to thoseshown in FIGS. 3B and 3C according to the first embodiment are carriedout, thus obtaining the structure of the semiconductor device shown inFIG. 8.

According to the semiconductor device fabricating method of the presentembodiment, it is possible to easily form the lower interconnect 16having the convex portions 16 a and 16 c at its bottom and sidesurfaces, respectively. Besides, in this structure, the convex portions16 a and 16 c have the function of gettering voids. Therefore, itbecomes possible to more effectively suppress an increase in contactresistance caused by concentrative gettering of voids in a region of thelower interconnect 16 (within the copper film 15) in contact with theupper plug 22 a.

Fifth Embodiment

FIG. 10 is a cross-sectional view illustrating the structure of asemiconductor device according to a fifth embodiment of the presentinvention. As shown in FIG. 10, the semiconductor device of the presentembodiment includes: a substrate 10 on which semiconductor elements (notshown) such as a large number of transistors are formed; a lowerinterlayer dielectric film 11 provided on the substrate 10; a lowerinterconnect groove 13 formed in the lower interlayer dielectric film11; a lower barrier metal layer 14 formed along a wall surface of thelower interconnect groove 13; a copper film 15 for filling the lowerinterconnect groove 13; a barrier metal layer 30 formed on the copperfilm 15; an upper interlayer dielectric film 17 provided on the lowerinterlayer dielectric film 11 and on the barrier metal layer 30; aconnection hole 18 formed in the upper interlayer dielectric film 17 andan upper interconnect groove 19 formed thereon; an upper barrier metallayer 20 formed along wall surfaces of the connection hole 18 and theupper interconnect groove 19; and a copper film 21 for filling theconnection hole 18 and the upper interconnect groove 19. A lowerinterconnect 16 is made up of the copper film 15 and the lower barriermetal layer 14 which fill the lower interconnect groove 13. On the otherhand, the upper interconnect groove 19 is formed in an extensive regionof the upper interlayer dielectric film 17 including the connection hole18. Further, portions of the upper barrier metal layer 20 and the copperfilm 21 filled in the connection hole 18 constitute an upper plug 22 a,while another portions of the upper barrier metal layer 20 and thecopper film 21 filled in the upper interconnect groove 19 constitute anupper interconnect 22 b. The upper plug 22 a and the upper interconnect22 b constitute an upper interconnect layer 22. Alternatively, as in thefirst through fourth embodiments, a silicon nitride film may be formedon the lower interlayer dielectric film 11 and the barrier metal layer30, and the upper interlayer dielectric film 17 may be formed on thesilicon nitride film.

The semiconductor device of the present embodiment is characterized inthat the barrier metal layer 30 which is a stress-relieving conductorfilm made of TaN and having a thickness of 50 nm is provided between thecopper film 15 of the lower interconnect 16 and the upper plug 22 a.Furthermore, the barrier metal layer 30 is formed on the copper film 15so as to be flush with the upper surface of the lower interlayerdielectric film 11. The barrier metal layer 30 has the function ofpreventing oxidation of the copper film 15 in the lower interconnect 16,and the function of relieving stress in the contact area between thecopper film 15 and the upper plug 22 a.

Also in the present embodiment, the thickness and planar size of thelower interconnect 16 are similar to those of the lower interconnect 16according to the first embodiment. In the conventional structure, it isknown that if the lower interconnect groove 13 has a width equal to orgreater than 0.25 μm and a length equal to or greater than 1 μm, a voidconcentration region is likely to be formed, in particular, in the lowerinterconnect 16.

The present embodiment is applicable to the substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 10, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 16. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the shape of the lower interconnect16 described in the present embodiment.

In the semiconductor device of the present embodiment, the barrier metallayer 30 for covering the copper film 15 of the lower interconnect 16 isprovided, thus relieving localized stress in the contact area betweenthe lower interconnect 16 and the upper plug 22 a. Accordingly, itbecomes possible to prevent voids from being concentratedly gettered ina region of the lower interconnect 16 in contact with the upper plug 22a.

Hereinafter, a method for fabricating the semiconductor device accordingto the present embodiment will be described. FIGS. 11A through 11D arecross-sectional views illustrating the process for fabricating thesemiconductor device of the present embodiment.

First, in the step shown in FIG. 11A, the steps substantially similar tothose shown in FIGS. 5A, 5C and 5D according to the second embodimentare carried out, thus forming a lower interlayer dielectric film 11 anda lower interconnect 16.

Next, in the step shown in FIG. 11B, a known lithography process isperformed to form a resist film Re5 having an opening for exposing theupper surface of a copper film 15 in the lower interconnect 16. Then,the copper film 15 is dry-etched using the resist film Re5 as a mask,thus removing a portion of the copper film 15 to a depth of 50 nm. Inthis case, the lower interlayer dielectric film 11 and lower barriermetal layer 14 may also be partially removed at the same time.

Subsequently, in the step shown in FIG. 11C, a barrier metal layer 30formed of a TaN film with a thickness of 100 nm is deposited on thelower interconnect 16 (the lower barrier metal layer 14 and the copperfilm 15) and on the lower interlayer dielectric film 11 by a sputteringprocess, for example.

Thereafter, in the step shown in FIG. 11D, the barrier metal layer 30 ispartially removed by a CMP process until the upper surface of the lowerinterlayer dielectric film 11 is exposed. Thus, the structure in whichthe barrier metal layer 30 is provided on the copper film 15 isobtained. Consequently, the barrier metal layer 30 is formed only in theremoved region that has been etched in the step shown in FIG. 11B, andis thus formed mainly on the copper film 15.

Although the subsequent steps are not shown, the steps similar to thoseshown in FIGS. 3B and 3C according to the first embodiment are carriedout, thus obtaining the structure of the semiconductor device shown inFIG. 10.

According to the semiconductor device fabricating method of the presentembodiment, the structure in which the barrier metal layer 30 isprovided on the copper film 15 is easily obtained. Besides, in thisstructure, it becomes possible to relieve stress in the contact areabetween the lower interconnect 16 (within the copper film 15) and theupper plug 22 a, and thus it becomes possible to suppress an increase incontact resistance caused by concentrative gettering of voids in aregion of the lower interconnect 16 (within the copper film 15) incontact with the upper plug 22 a.

Alternatively, instead of the barrier metal layer 30 formed of a TaNfilm, the semiconductor device may be provided with a stress-relievingconductor film made of a conductor material that does not have thefunction of preventing the passage of oxygen, and a silicon nitride filmmay further be formed thereon. Even in such a case, the effects similarto those of the present embodiment can be achieved.

Sixth Embodiment

FIG. 12 is a cross-sectional view illustrating the structure of asemiconductor device according to a sixth embodiment of the presentinvention. As shown in FIG. 12, the semiconductor device of the presentembodiment includes: a substrate 10 on which semiconductor elements (notshown) such as a large number of transistors are formed; a lowerinterlayer dielectric film 11 provided on the substrate 10; a lowerinterconnect groove 13 formed in the lower interlayer dielectric film11; a lower barrier metal layer 14 formed along a wall surface of thelower interconnect groove 13; a Si-containing copper film 35 for fillingthe lower interconnect groove 13; a silicon nitride film 24 provided onthe lower interlayer dielectric film 11 and on the Si-containing copperfilm 35; an upper interlayer dielectric film 17 provided on the siliconnitride film 24; a connection hole 18 formed in the upper interlayerdielectric film 17 and an upper interconnect groove 19 formed thereon;an upper barrier metal layer 20 formed along wall surfaces of theconnection hole 18 and the upper interconnect groove 19; and a copperfilm 21 for filling the connection hole 18 and the upper interconnectgroove 19. A lower interconnect 36 is made up of the Si-containingcopper film 35 and the lower barrier metal layer 14 which fill the lowerinterconnect groove 13. On the other hand, the upper interconnect groove19 is formed in an extensive region of the upper interlayer dielectricfilm 17 including the connection hole 18. Further, portions of the upperbarrier metal layer 20 and the copper film 21 filled in the connectionhole 18 constitute an upper plug 22 a, while another portions of theupper barrier metal layer 20 and the copper film 21 filled in the upperinterconnect groove 19 constitute an upper interconnect 22 b. The upperplug 22 a passes through the silicon nitride film 24 and comes intocontact with the Si-containing copper film 35 of the lower interconnect16. The upper plug 22 a and the upper interconnect 22 b constitute anupper interconnect layer 22.

The semiconductor device of the present embodiment is characterized inthat the lower interconnect 36 has the Si-containing copper film 35.Also in the present embodiment, the thickness and planar size of thelower interconnect 36 are similar to those of the lower interconnect 16according to the first embodiment.

The present embodiment is applicable to the substrate 10 even if anotherlower interlayer dielectric film and/or interconnect layer are/isfurther provided. In the present embodiment, as indicated by the brokenlines in FIG. 12, another lower interconnect and/or another plug thatreaches the semiconductor substrate are/is further provided below thelower interconnect 36. In general, the semiconductor device is oftenprovided with three or more interconnect layers; however, each of theseinterconnect layers preferably has the structure of the lowerinterconnect 36 described in the present embodiment.

In the semiconductor device of the present embodiment, the lowerinterconnect 36 is provided with the Si-containing copper film 35, andthus voids are also gettered by the Si-containing copper film 35 in thelower interconnect 36. Therefore, it becomes possible to prevent voidsfrom being concentratedly gettered in a region of the lower interconnect36 in contact with the upper plug 22 a.

Hereinafter, a method for fabricating the semiconductor device of thepresent embodiment will be described. FIGS. 13A through 13C arecross-sectional views illustrating the process for fabricating thesemiconductor device of the present embodiment.

First, in the step shown in FIG. 13A, the steps substantially similar tothose shown in FIGS. 5A, 5C and 5D according to the second embodimentare carried out, thus forming a lower interlayer dielectric film 11, alower barrier metal layer 14 and a copper film 15.

Next, in the step shown in FIG. 13B, a known lithography process isperformed to form a resist film Re6 having an opening for exposing theupper surface of the copper film 15. Then, Si ions (Si⁺) are implantedinto the copper film 15 using the resist film Re6 as a mask, thusforming a Si-containing copper film 35. In this case, Si ions areimplanted at an implant energy of about 180 keV to about 250 keV, forexample, and an implant dose of about 1×10¹⁴ cm⁻². If the implant energyis 180 keV, the implant depth of Si atoms is about 0.10 μm, and if theimplant energy is 250 keV, the implant depth of Si atoms is about 0.15μm. Furthermore, if the implant dose is 1×10¹⁴ cm⁻², the number of Siatoms in the copper film is approximately 1×10¹⁹/cm³ (atomic percentageis approximately 0.01%).

In this step, Si ions may be implanted into a part of the lower barriermetal layer 14 at the same time, or Si ions do not have to be implantedinto a part of the copper film 15.

Subsequently, in the step shown in FIG. 13C, the resist film Re6 isremoved by ashing. Thus, a lower interconnect 36 having theSi-containing copper film 35 is obtained.

Although the subsequent steps are not shown, the steps similar to thoseshown in FIGS. 3B and 3C according to the first embodiment are carriedout, thus obtaining the structure of the semiconductor device shown inFIG. 12.

According to the semiconductor device fabricating method of the presentembodiment, the lower interconnect 36 having the Si-containing copperfilm 35 can be easily formed. Besides, in this structure, the Si in theSi-containing copper film 35 has the function of gettering voids.Therefore, it becomes possible to suppress an increase in contactresistance caused by concentrative gettering of voids in a region of thelower interconnect 36 (within the Si-containing copper film 35) incontact with the upper plug 22 a.

In the step shown in FIG. 13B, instead of Si, other dopant having thefunction of gettering voids (such as Ge, C, Al, Ta, Ti, W, Ni or Co) mayalternatively be implanted into the copper film 15. Even in such a case,the effects similar to those of the present embodiment can be achieved.

Modifications of Foregoing Embodiments

In each of the foregoing embodiments, principal portions of the lowerinterconnect 16 (or 36) and the upper interconnect layer 22 are eachformed by a copper film. Alternatively, the inventive semiconductordevice may be provided with an interconnect whose principal portion isformed by a film made of a conductive material other than copper, suchas a polysilicon film, an aluminum film, an aluminum alloy film or atungsten film. Even in such a case, the effects similar to those of eachof the foregoing embodiments can be achieved.

Instead of the silicon nitride film 24 in each of the foregoingembodiments, an SiON film, an SiOF film, an SiC film, an SiCF film orthe like may alternatively be used. If there is almost no possibility ofoxidation of the lower interconnect, or if no problem is caused by theoxidation, it is unnecessary to provide the silicon nitride film or amember equivalent to the silicon nitride film.

Suppose no concave portions are provided at the wall surface of thelower interconnect groove. In that case, if the convex portions areprovided at the upper surface of the lower interconnect, stress isgenerated in these portions; therefore, it is possible to achieve theeffect of distributing the regions where voids are gettered, which isthe basic effect of the present invention.

1-17. (canceled)
 18. A semiconductor device comprising: a substrate provided with a semiconductor element; an interlayer dielectric film provided on the substrate; an interconnect groove provided in the interlayer dielectric film; and an interconnect provided within the interconnect groove and having convex or concave portions at least at one of its side surfaces and bottom surface.
 19. The semiconductor device according to claim 18, wherein the interconnect groove is provided at its bottom surface with concave or convex portions, and wherein the convex or concave portions of the interconnect have shapes corresponding to those of the concave or convex portions of the interconnect groove.
 20. The semiconductor device according to claim 18, wherein the interconnect groove is provided at its side surfaces with concave or convex portions, and wherein the convex or concave portions of the interconnect have shapes corresponding to those of the concave or convex portions of the interconnect groove.
 21. The semiconductor device according to claim 18, wherein the interconnect groove is provided at its wall surface with concave and convex portions having irregular shapes, and wherein the convex portions of the interconnect have shapes corresponding to those of the concave portions in the concave and convex portions of the interconnect groove.
 22. The semiconductor device according to claim 18, wherein the interconnect includes a portion formed by a copper film.
 23. The semiconductor device according to claim 18, wherein the interconnect comprises: a barrier metal layer formed along side surfaces and a bottom surface of the interconnect groove; and a first copper film formed in the interconnect groove via the barrier metal layer.
 24. The semiconductor device according to claim 19, wherein the interconnect comprises: a barrier metal layer formed along side surfaces and a bottom surface of the interconnect groove; and a copper film formed in the interconnect groove via the barrier metal layer.
 25. The semiconductor device according to claim 18, wherein at a bottom surface of the interconnect, a lower interconnect and/or a plug that reaches the substrate are/is provided.
 26. The semiconductor device according to claim 19, wherein at a bottom surface of the interconnect, a lower interconnect and/or a plug that reaches the substrate are/is provided.
 27. The semiconductor device according to claim 23, wherein at a bottom surface of the interconnect, a lower interconnect and/or a plug that reaches the substrate are/is provided.
 28. The semiconductor device according to claim 24, wherein at a bottom surface of the interconnect, a lower interconnect and/or a plug that reaches the substrate are/is provided. 